/ Samsung Electronics Semiconductor Newsroom

Samsung Electronics is set to implement a 2-nanometer (GAA) foundry process for the base die of its next-generation high-bandwidth memory (HBM), HBM5. This move, following the introduction of cutting-edge processes in HBM4, aims to bolster the company's competitiveness in artificial intelligence (AI) semiconductors and accelerate its strategy in the AI and high-performance computing (HPC) markets.

According to Samsung Electronics' semiconductor newsroom on Monday, Koo Ja-hum, Vice President and Head of Technology Development at Samsung Foundry, stated that it anticipates HBM5 to deliver over 50% improvement in operational speed compared to its predecessor, HBM4E. It's planning to incorporate a 2-nanometer process with a GAA structure for the base die and implement silicon through-vias (TSVs) with even higher integration.

In the HBM stacked structure, the base die is a logic chip positioned beneath the core die. It functions as a high-speed interface, facilitating data exchange between external processors like graphic processing units (GPUs) and central processing units (CPUs) and the HBM. Since HBM4, the shift from traditional memory processes to foundry processes has established the base die as a crucial component influencing HBM's performance and power efficiency.

Samsung made history earlier this year by mass-producing HBM4 in February, followed by the shipment of 12-layer HBM4E samples in May. Both HBM4 and HBM4E base dies utilized a proven 4-nanometer fourth-generation process for mass production and yield.

Koo highlighted that the 4-nanometer process offers diverse design options, optimizing area and performance for specific design goals. He explained that HBM4E incorporates highly integrated, ultra-high-performance devices to achieve speeds exceeding 14 Gbps, while optimizing metal wiring layers to enhance power consumption and heat dissipation.

Samsung emphasized its competitive edge in its turnkey production system, where memory, foundry, and TSP (semiconductor packaging) teams collaborate from the initial design phase. This approach enables simultaneous optimization of speed, power consumption, heat generation, and yield.

The company's foundry business is also expanding, with a focus on AI semiconductors. Following its world-first mass production of GAA-based 3-nanometer chips, Samsung initiated mass production of first-generation 2-nanometer processes last year. The second half of this year will see the application of an improved second-generation 2-nanometer process to mobile products, boasting enhanced performance and yield.

Koo noted that last year's breakthrough order for 2-nanometer automotive semiconductors from Tesla has paved the way for additional contracts from major clients in AI, HPC, and cloud service providers (CSPs). The 4-nanometer process is also gaining recognition for its competitive edge in HBM4 base dies and AI/HPC semiconductors for American AI companies.

Looking ahead, Samsung plans to broaden its applications beyond AI and HPC to include automotive and robotics sectors. The company aims to strengthen its competitive edge in one-stop solutions combining advanced packaging and HBM, while continuing to develop next-generation semiconductor technologies such as silicon photonics for data centers and co-packaged optics (CPO).

Reflecting on the HBM4 base die development, Koo shared that the company-wide task force achieved all performance and yield targets from the first sample, enabling them to establish mass production systems in just three months. Leveraging the process experience gained from HBM4, it's confident in maintaining the technological leadership with HBM5.

Samsung Electronics is set to implement a 2-nanometer (GAA) foundry process for the base d …

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